In circuit design, we are generally concerned about the quality of the signal, but sometimes we are often limited to the signal line for research, and the power and ground as the ideal situation to deal with, although this can simplify the problem, but in high-speed design This simplification is no longer feasible. Although the direct result of circuit design is manifested in signal integrity, we must not neglect the power integrity design. Because power integrity directly affects the signal integrity of the final PCB. Both power integrity and signal integrity are closely related, and in many cases, the main cause of signal distortion is the power system. For example, the ground bounce noise is too large, the design of the decoupling capacitor is not suitable, the loop influence is serious, the division of multiple power/ground planes is not good, the formation design is unreasonable, the current is not uniform, etc.

1) Power distribution system

Power integrity design is a very complicated matter, but how to control the impedance between the power system (power and ground plane) in recent years is the key to the design. In theory, the lower the impedance between the power systems, the better, the lower the impedance, the smaller the noise amplitude, and the smaller the voltage loss. In the actual design, we can determine the target impedance we want to achieve by specifying the maximum voltage and power variation range. Then, by adjusting the relevant factors in the circuit, the impedance (frequency-dependent) target impedance of each part of the power system is approached.

2)Ground bounce

When the edge rate of a high-speed device is less than 0.5 ns, the data exchange rate from the large-capacity data bus is particularly fast, and when it generates strong ripples in the power supply layer that are sufficient to affect the signal, power supply instability occurs. When the current through the ground loop changes, a voltage is generated due to the loop inductance. When the rising edge is shortened, the current change rate increases, and the ground bounce voltage increases. At this point, the ground plane (ground) is no longer an ideal zero level, and the power supply is not the ideal DC potential. When the gate of the simultaneous switch increases, the ground bounce becomes more serious. For a 128-bit bus, there may be 50_100 I/O lines switching on the same clock edge. At this time, the inductance of the power supply and the ground return that is fed back to the I/O driver that is switched at the same time must be as low as possible. Otherwise, a voltage brush will appear when it is connected to the same ground. Ground bounce can be seen everywhere, such as chip, package, connector or circuit board may rebound, resulting in power integrity issues.

From the perspective of technology development, the rising edge of the device will only decrease, and the width of the bus will only increase. The only way to keep ground bounced is to reduce the power and ground distribution inductance. For the chip, it means moving to an array of wafers, placing the power and ground as much as possible, and the wiring to the package is as short as possible to reduce inductance. For packaging, it means moving the layer package to make the ground plane spacing of the power supply closer, as used in BGA packages. For connectors, it means using more ground pins or redesigning the connectors to have internal power and ground planes, such as connector-based ribbon cords. For a board, it means that the adjacent power and ground planes are as close as possible. Since the inductance is proportional to the length, making the connection of the power supply and ground as short as possible will reduce the ground noise.

3) Decoupling capacitor

We all know that adding some capacitor between the power supply and ground can reduce the noise of the system, but how much capacitance is added to the circuit board? How large is the capacitance of each capacitor? What position is better for each capacitor? Similar to these problems We generally don’t think about it seriously, just by the experience of the designer, sometimes even think that the less the capacitor, the better. In high-speed design, we must consider the parasitic parameters of the capacitor, quantitatively calculate the number of decoupling capacitors and the capacitance of each capacitor and the specific position of the placement, to ensure that the impedance of the system is within the control range, a basic principle is the need for decoupling capacitors, can not be less, the excess capacitor, can’t be more.